1. 镐庢牱灏哅atlab浜х敓镄勬暟鎹浼犲叆FPGA
鍙浠ュ熷姪Matlab镄勪覆鍙ｉ氲镄勫嚱鏁般傜数鑴戜笂鍙浠ヨ喘涔颁竴涓猆SB-UART杞鎹㈠櫒涓峄PGA杩炴帴銆
2. 浣犵殑AD鏁版嵁瀛桦湪FPGA涓铡绘槸杩欎箞瀹炵幇镄勶纻锛
AD鑺鐗囨槸TLC549锛孍P2c5t144鍗旷嚎镄勪覆琛屾暟鎹浼犻併
鍏堜緥鍖栦竴涓狲dram controller锛屽啀镓扑釜testbench锛岀劧钖庡啀build image锛屽啀涓婃澘娴嬭瘯銆傝繖鍙鑳芥槸姣旇缉蹇镄勬柟寮忎简銆傛渶濂借佸箂dram镄勮诲啓镞跺簭姣旇缉镡熸倝锛岀劧钖庝緥鍖栫殑controller镓嶈兘姣旇缉闱犺氨锛屽傛灉鑳芥闷鍒皊dram镄刡fm妯″瀷锛岄偅鍙鑳芥洿濂姐
AD杈揿嚭镄勬暟鎹鐩存帴杩汧PGA锛屼笉绠℃槸楂橀烝D镄勪覆琛岃緭鍑鸿缮鏄骞惰屽樊鍒嗘暟鎹锛孎PGA镄処O閮藉彲浠ユ敮鎸併傝繘FPGA钖庢暟鎹鍙浠ュ瓨鍦‵PGA镄凚RAM閲岄溃銆
FPGA锛团ield锛峆rogrammable Gate Array锛夛纴鍗崇幇鍦哄彲缂栫▼闂ㄩ樀鍒楋纴瀹冩槸鍦≒AL銆丢AL銆丆PLD绛夊彲缂栫▼鍣ㄤ欢镄勫熀纭涓婅繘涓姝ュ彂灞旷殑浜х墿銆傚畠鏄浣滀负涓撶敤闆嗘垚鐢佃矾锛圆SIC锛夐嗗烟涓镄勪竴绉嶅崐瀹氩埗鐢佃矾钥屽嚭鐜扮殑锛屾棦瑙ｅ喅浜嗗畾鍒剁数璺镄勪笉瓒筹纴鍙埚厠链崭简铡熸湁鍙缂栫▼鍣ㄤ欢闂ㄧ数璺鏁版湁闄愮殑缂虹偣銆
3. xilinx镄刡it鏂囦欢镙煎纺濡备綍鍐椤叆FPGA
褰扑綘𨱍虫妸bit鏂囦欢阃氲繃绋嫔簭鍐椤叆fpga镄勬椂鍊欙纴浣犱细鍙戠幇镐绘槸涓嶅广傚洜涓篵it格寮忔槸bitgen鐢熸垚镄刯tag鐢ㄧ殑格寮忋
浣跨敤impact宸ュ叿鑳藉熷畬鎴愯浆鎹銆
琛5-19 甯哥敤镄刋ilixn FPGA閰岖疆鏂囦欢格寮忓垪琛
濡傛灉浣犳兂阃氲繃浠ｇ爜鐩存帴璇诲彇锛屽氨闇瑕佷简瑙ｆ枃浠剁粨鏋勪简銆傜绣涓婃悳浜嗘悳锛屾病链夎繖绫荤殑搴旂敤銆傜壒灏嗙爷绌舵垚鏋滃啓涓嬫潵锛屼负钖庢潵浜轰娇鐢ㄦ柟渚裤
ushort siglengthchar[] sig
ushort version[00 01]
char a// type {a-e}
ushort project name length
char[] project namechar b
ushort xilinx fpga name length
char[] xilinx fpga namechar c
ushort date length
char[] date namechar d
ushort time length
char[] time namechar e